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Planar MOSFETs vs. FinFETs


By
Nasir Alfaraj

October 26, 2016 - Posted in Discussion
​The metal-oxide-semiconductor field-effect transistor (MOSFET) is the basic element used in designing and fabricating modern high-performance integrated circuits (ICs) for switching or amplifying electronic signals. MOSFETs enjoy considerable advantages in terms of integration feasibility: Large-scale production and easy prototyping, relative ease of scaling at minimum cost and maximum reliability, and low standby power consumption are the prime reasons for MOSFET’s dominance in today’s digital circuits and system-on-chip (SoC) industry. Other types of transistors (such as the bipolar junction transistor (BJT)) are typically employed in ultra-high-performance integrated circuits. The nonplanar, nanoscale fin field-effect transistor (FinFET) is a three-dimensional (3D)-implementation of the MOSFET, with the conducting channel elevated so the gate can surround it on three sides.

Figure 1 (left) shows a scanning electron microscopy (SEM) micrograph of a silicon-based MOSFET cross section. It displays the silicon substrate, the heavily doped drain (D) and source (S) regions, the insulators between the channel and gate, and the thin gate insulator. Figure 2 shows an SEM micrograph of a FinFET. The area between the source and drain is called the channel. Figure 1 (right) shows the circuit schematic of the MOSFET, where the gate terminal controls the transistor (ON or OFF state) while, in the ON state, the channel current (IDS) flows between the source and drain. Hence, a MOSFET can be thought of as a voltage-controlled current source. For an n-channel MOSFET (nMOS), the substrate used is a p-type silicon substrate and the source and drain regions are heavily doped n-type regions, while for a p-channel MOSFET (pMOS), the substrate is an n-type silicon substrate with heavily doped p-type drain and source regions.

 
Figure 1. Cross-section SEM micrograph (left) and circuit schematic (right) of a planar MOSFET [1].

 
Figure 2. Cross-section SEM micrographs of a FinFET (from http://techon.nikkeibp.co.jp/​)

The FinFET offers considerable advantages over the planar MOSFETs:
  1. Higher output current per input voltage.
  2. Higher switching speeds and lower power consumption due to lower equivalent input capacitance and channel quantization effects (confined density of states leads to better current density).
  3. Better on/off contrast due to channel quantization effects.
  4. Channel quantization effects also reduce short-channel effects due to more effective physical separation of the source and drain regions.
FinFET measurements conducted in the Nanofabrication Core Lab at KAUST revealed the following:
  1. Usage of TiN as a FinFET gate electrode has contributed to low and stable threshold voltage (VTH) values. This is because the TiN/high-κ interfaces exhibit less trapped charges resulting from interfacial reactions1. Also, TiN exhibits work function values between 4.2 eV and 4.5 eV, which is very close to the electron affinity of a silicon crystal surface (about 4.05 eV), which will result in lower VTH.2
  2. Low variation in FinFET device VTH values is attributed to dielectric thickness uniformity.
  3. Excellent performance evidenced by low subthreshold swing values (especially in FinFET nMOS devices) is due to the use of silicon-on-insulator (SOI) technology as a substrate and the FinFET structure.3

References:

[1] Wang, X., Peterson, J., Majhi, P., Gardner, M. I., & Kwong, D. L. (2005). Impacts of gate electrode materials on threshold voltage (V th) instability in nMOS HfO 2 gate stacks under DC and AC stressing. IEEE Electron Device Letters, 26(8), 553-556.

[2] Lima, L. P., Moreira, M. A., & Diniz, J. A. (2012). Titanium nitride as promising gate electrode for MOS technology. physica status solidi (c), 9(6), 1427-1430.

[3] Shih, K. H., & Chui, C. O. (2008, October). The low subthreshold swing possibility with asymmetries in double-gate SOI MOSFET. In 2008 IEEE International SOI Conference.

[4] Hisamoto, D., Lee, W. C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T-. J., Bokor, J., & Hu, C. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47(12), 2320-2325.

[5] Ghoneim, M. T., Alfaraj, N., Torres-Sevilla, G. A., Fahad, H. M., & Hussain, M. M. (2016). Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS. IEEE Transactions on Electron Devices​, 63(7), 2657-2664.

[6] Rojas, J. P., Torres Sevilla, G. A., Alfaraj, N., Ghoneim, M. T., Kutbee, A. T., Sridharan, A., & Hussain, M. M. (2015). Nonplanar Nanoscale Fin Field Effect Transistors on Textile, Paper, Wood, Stone, and Vinyl via Soft Material-Enabled Double-Transfer Printing. ACS nano, 9(5), 5255-5263.

[7] Alfaraj, N., Hussain, A. M., Sevilla, G. A. T., Ghoneim, M. T., Rojas, J. P., Aljedaani, A. B., & Hussain, M. M. (2015). Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform. Applied Physics Letters, 107(17), 174101.

[8] Ghoneim, M. T., Alfaraj, N., Sevilla, G. A. T., Fahad, H. M., & Hussain, M. M. (2015, June). Out-of-plane strain effect on silicon-based flexible FinFETs. In 2015 73rd Annual Device Research Conference (DRC) (pp. 95-96). IEEE.

[9] Ghoneim, M. T., Alfaraj, N., Sevilla, G. A. T., & Hussain, M. M. (2015, July). Ultra-high density out-of-plane strain sensor 3D architecture based on sub-20 nm PMOS FinFET. In Nanotechnology (IEEE-NANO), 2015 IEEE 15th International Conference on (pp. 1422-1425). IEEE.
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